Associate Professor
Chinese Academy of Sciences


I am an Associate Professor at the Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). My research interest focuses on FPGAs (Field Programmable Gate Arrays) related technologies, which span multiple areas including FPGA-based reconfigurable hardware accelerators, FPGA-based emulation and prototyping, next-gen FPGA architecture, EDA algorithms and tools for efficient FPGA configuration, and FPGA applications in networking, arithmetic circuits and more.


My broader research group (led by Professor Yungang Bao) at ICT focuses on open-source chip design and verification using agile methodologies. Therefore I am now particularly interested in FPGA-accelerated agile design and verification for digital circuit designs including processors and accelerators.


I received my Ph.D. from Imperial College London, under the supervision of Professor George A. Constantinides. I then worked as an FPGA design engineer at Intel for several years, providing system-level solutions for top-tier cloud customers. I was heavily involved in developing Intel’s first IPU (Infrastructure Processing Unit), codenamed Big Springs Canyon.


I'm Hiring!

For students: I normally have one or two positions available for Master student admission each year, please reach out early as the application can be competitive.

For researchers: There are post-doc positions open in the group, and I am constantly hiring visiting students & interns.

If you are interested in doing research with me, please email me your most updated CV at: shikan[at]ict.ac.cn

News


  • May 2025: Shuoxiang Xu successfully passed the Master Viva. Congratulations Shuoxiang!
  • April 2025: Four posters accepted to appear at RISC-V Summit Europe 2025, see you all in Paris!
  • April 2025: Paper on SmartNIC-accelerated image provisioning for coldstart in cloud datacenters accpeted at USENIX ATC 2025.
  • December 2024: Two full papers on agile HLS verification accpeted by FPGA 2025! We proposed agile verification methods targeting HLS designs from different perspectives, all building on the ENCORE platform (published on FPGA'23) for FPGA acceleration. Congrats to Shuoxiang, Linaghui and Zijian!

  • Selected Publications


  • Changlong Li, Yu Liang, Rachata Ausavarungnirun, Zongwei Zhu, Liang Shi, Chuan Jason Xue
    "ICE: Collaborating Memory and Process Management for User Experience on Resource-limited Mobile Devices"
    Proceedings of the 18th European Conference on Computer Systems (EuroSys 2023), Rome, Italy, May 2023.
  • Kevin Chang, Rachata Ausavarungnirun, Chris Fallin, Onur Mutlu.
    "Adaptive Cluster Throttling: Improving High-Load Performance in Bufferless On-Chip Networks".
    SAFARI Technical Report No. 2011-006. September 6, 2011.
  • Academic Services


  • Computer Organization (at University of Chinese Academy of Sciences, Spring 2025)
  • Program Committee: FPGA 2023-2025, DAC 2025, FCCM 2023-2025, FPT 2023-2025
  • Organizing Committee: FPT 2024 (Publicity Chair)
  • Reviewer for: ASPLOS (2016-2018), DAC (2015-2016), DATE (2015), DSN (2016, 2019), FAST (2019), HPCA (2015, 2017-2018), ICCD (2013, 2015), ISCA (2013, 2017, 2019), MICRO (2013, 2014, 2017, 2019), PACT (2013, 2018), PLDI (2017), SBAC-PAD (2016), SPAA (2015), ACM Transactions on Architecture and Code Optimization (2014-2019), IEEE Computer Architecture Letters (2018-2019), IEEE Transactions on Very Large Scale Integration (2018-2019), IEEE Transactions on parallel and Distributed Systems (2016), IEEE Transactions on Computing (2016, 2019), IEEE Transactions on Circuits and Systems (2019)