Kan Shi Associate Professor, ICT CAS

Publications

My selected publications in agile verification, FPGA, and reconfigurable computing.

  • Lyra: A Hardware-Accelerated RISC-V Verification Framework with Generative Model-Based Processor Fuzzing
    Huo, Juncheng and Gao, Yunfan and Liu, Xinxin and Wang, Sa and Bao, Yungang and Gao, Xitong and Shi, Kan
    Proceedings of the 63rd Chips to Systems Conference (DAC) · 2026
  • TurboFuzz: FPGA Accelerated Hardware Fuzzing for Processor Agile Verification
    Zhong, Yang and Wu, Haoran and Li, Xueqi and Wang, Sa and Boland, David and Bao, Yungang and Shi, Kan
    Proceedings of the 32nd IEEE International Symposium on High-Performance Computer Architecture (HPCA) · 2026
  • Latency Insensitivity Testing for Dataflow HLS Designs
    Cheng, Jianyi and Wang, Lianghui and Jiang, Zijian and Bao, Yungang and Shi, Kan
    Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) · 2025
  • Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration
    Xu, Shuoxiang and Jiang, Zijian and Zhang, Yuxin and Boland, David and Bao, Yungang and Shi, Kan
    Proceedings of the 2025 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) · 2025
  • Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
    Jiang, Zijian and Zheng, Keran and Boland, David and Bao, Yungang and Shi, Kan
    Proceedings of the 30th Asia and South Pacific Design Automation Conference (ASP-DAC) · 2025
  • Poby: SmartNIC-accelerated Image Provisioning for Coldstart in Clouds
    Chang, Zihao and Zhu, Jiaqi and Sun, Haifeng and Xie, Yunlong and Shi, Kan and Sun, Ninghui and Bao, Yungang and Wang, Sa
    Proceedings of the 2025 USENIX Annual Technical Conference (USENIX ATC) · 2025
  • DUET: FPGA-Accelerated Differential Testing Framework for Efficient Processor Verification
    Zhang, Shoulin and Zhang, Ziqing and Bao, Yungang and Shi, Kan
    Proceedings of the 2nd International Symposium of Electronics Design Automation (ISEDA) · 2024
  • Efficient Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
    Jiang, Zijian and Zheng, Keran and Bao, Yungang and Shi, Kan
    Proceedings of the 2nd International Symposium of Electronics Design Automation (ISEDA) · 2024
  • Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration
    Zhang, Ziqing and Weng, Weijie and Li, Yaning and Cai, Lijia and Wang, Haoyu and Boland, David and Bao, Yungang and Shi, Kan
    Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) · 2024
  • ENCORE: Efficient architecture verification framework with FPGA acceleration
    Shi, Kan and Xu, Shuoxiang and Diao, Yuhan and Boland, David and Bao, Yungang
    Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA) · 2023
  • Functional Verification for Agile Processor Development: A Case for Workflow Integration
    Xu, YiNan and Yu, ZiHao and Wang, KaiFan and Wang, HuaQiang and Lin, JiaWei and Jin, Yue and Zhang, LinJuan and Zhang, ZiFei and Tang, Dan and Wang, Sa and Shi, Kan and Sun, Ninghui and Bao, Yungang
    Journal of Computer Science and Technology (JCST) · 2023
  • Towards developing high performance RISC-V processors using agile methodology
    Xu, Yinan and Yu, Zihao and Tang, Dan and Chen, Guokai and Chen, Lu and Gou, Lingrui and Jin, Yue and Li, Qianruo and Li, Xin and Li, Zuojun and Lin, Jiawei and Liu, Tong and Liu, Zhigang and Tan, Jiazhan and Wang, Huaqiang and Wang, Huizhe and Wang, Kaifan and Zhang, Chuanqi and Zhang, Fawang and Zhang, Linjuan and Zhang, Zifei and Zhao, Yangyang and Zhou, Yaoyang and Zhou, Yike and Zou, Jiangrui and Cai, Ye and Huan, Dandan and Li, Zusong and Zhao, Jiye and Chen, Zihao and He, Wei and Quan, Qiyuan and Liu, Xingwu and Wang, Sa and Shi, Kan and Sun, Ninghui and Bao, Yungang
    Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) · 2022
  • Design of approximate overclocked datapath
    Shi, Kan
    My PhD Thesis at Imperial College London · 2016
  • Imprecise datapath design: An overclocking approach
    Shi, Kan and Boland, David and Constantinides, George A
    ACM Transactions on Reconfigurable Technology and Systems (TRETS) · 2015
  • Evaluation of design trade-offs for adders in approximate datapath
    Shi, Kan and Constantinides, George A
    Proceedings of the HiPEAC Workshop on Approximate Computing · 2015
  • Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs
    Shi, Kan and Boland, David and Stott, Edward and Bayliss, Samuel and Constantinides, George A
    Proceedings of the The 51st Annual Design Automation Conference (DAC) · 2014
  • Efficient FPGA Implementation of Digit Parallel Online Arithmetic Operators
    Shi, Kan and Boland, David and Constantinides, George A.
    Proceedings of the International Conference on Field-Programmable Technology (FPT) · 2014
  • Overclocking datapath for latency-error tradeoff
    Shi, Kan and Boland, David and Constantinides, George A
    Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) · 2013
  • Accuracy-performance tradeoffs on an FPGA through overclocking
    Shi, Kan and Boland, David and Constantinides, George A
    Proceedings of the IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) · 2013
  • Delay test for diagnosis of power switches
    Khursheed, Saqib and Shi, Kan and Al-Hashimi, Bashir M and Wilson, Peter R and Chakrabarty, Krishnendu
    IEEE Transactions on Very Large Scale Integration Systems (TVLSI) · 2013

Open-source artifacts

We prioritize releasing datasets, scripts, and evaluation harnesses for reproducibility.

Project repositories Latest updates

Citation focus

If you would like a BibTeX entry or a preprint, please reach out directly.

Contact: shikan[at]ict.ac.cn