Research

My work explores how programmable hardware can accelerate design, verification, and deployment of next-generation digital systems. The group focuses on FPGA-based systems that support agile, cloud-scale hardware workflows.

FPGA-accelerated agile verification

Building ENCORE-inspired platforms to shorten design iteration loops, with emphasis on HLS verification and co-simulation.

Reconfigurable hardware architectures

Exploring fabrics, interconnects, and configuration workflows for scalable FPGA deployments.

EDA algorithms and tooling

Placement, routing, and compilation innovations to reduce runtime and improve quality of results.

Cloud and network acceleration

SmartNIC and IPU co-design for programmable data planes and infrastructure services.

Methods

Agile design loops
Rapid prototyping with automated verification and runtime observability.
System-level evaluation
Workload-driven evaluation across cloud, network, and edge environments.
Open-source collaboration
Contributions to shared tooling with cross-institution partners.

Selected directions

Recent work centers on agile verification for HLS, FPGA emulation for processor pipelines, and hardware acceleration for cloud infrastructure services.

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